Patent · US Active

Method and device for error detection for a cache memory and corresponding cache memory

US7831889B2 · kind B2 · utility

0Cited by

11References

12Claims

0Family size

Assignee

Robert Bosch GmbH · DE

Inventors

Reinhard Weiberle · Lambach, DE
Bernd Mueller · Leonberg, DE
Thomas Kottke · Ehningen, DE

Key dates

Filing date	Jun 18, 2004
Grant date	Nov 9, 2010
Priority date	—
Expiry date	Dec 2, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1064
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for error detection in a cache memory for storing data, the access to the data stored in the cache memory taking place by addresses assigned to them, wherein for the addresses assigned to the stored data, at least one first test signature made up of at least one first signature bit is generated and also stored in the cache memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.