Manufacturing a clock distribution network in an integrated circuit
US7831945B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | May 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.