Nanometric structure and corresponding manufacturing method
US7834344B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Sep 3, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/781
Abstract
A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.