Memory array of non-volatile electrically alterable memory cells for storing multiple data
US7834388B2 · kind B2 · utility
6Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2006 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Feb 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.