3-D channel field-effect transistor, memory cell and integrated circuit

US7834395B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Dietmar Temmler · Dresden, DE
• Alexander Sieck · Dresden, DE

Key dates

• Filing date: Feb 13, 2007
• Grant date: Nov 16, 2010
• Expiry date: Dec 14, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6213

Abstract

A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source and drain regions. A first insulator structure is provided between the gate electrode and the source region. A second insulator structure is provided between the gate electrode and the drain region. The first and the second insulator structures are formed asymmetric and may be adapted to different requirements. The asymmetric approach may provide longer transistor channels, a lower resistance of the gate electrode and smaller footprints for 3D-channel-transistors of, for example, array and support transistors in memory cells or power applications.