Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate
US7834456B2 · kind B2 · utility
24Cited by
10References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 20, 2009 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.