Failsafe and tolerant driver architecture and method
US7834653B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2009 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Oct 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.