Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
US7834684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2008 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | May 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.