Phase error cancellation
US7834706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Mar 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.