Display processing line buffers incorporating pipeline overlap
US7834873B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2006 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | May 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/21
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.