Semiconductor memory device and semiconductor memory system
US7835169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2009 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Jun 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2257
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.