Method and system for achieving power optimization in a hierarchical netlist
US7836418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2008 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.