Method and system for partitioning integrated circuits
US7836419B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Oct 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.