Maintaining output I/O signals within an integrated circuit with multiple power domains
US7839016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided with a power domain which can be selectively powered-up or powered-down. An output circuitry serving to buffer a signal generated by the core circuitry within such a power domain has its own output power supply voltage. An adaptive voltage sensing circuit senses when the core power supply voltage to the core circuitry falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a pulse with its value stored within a mode latch indicating whether or not retention is required. Thus, when the adapted voltage sensing circuitry itself senses the voltage level for the core circuitry falling below the threshold, it activates the retention operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.