Counter and Frequency divider thereof
US7839187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2009 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.