Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment
US7839194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Feb 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.