Phase locked loop and method for adjusting the frequency and phase in the phase locked loop
US7839221B2 · kind B2 · utility
7Cited by
3References
8Claims
0Family size
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Key dates
| Filing date | Jun 4, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Oct 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.