Architecture for multi-stage decoding of a CABAC bitstream
US7839311B2 · kind B2 · utility
25Cited by
3References
27Claims
0Family size
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Key dates
| Filing date | Aug 22, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Techniques for optimizing the Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream decoding are disclosed. In one configuration, a device has a first processing circuit operative to decode a Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream into an intermediate signal having a CABAC decoded standard format and a decoded order. A second processing circuit decodes the intermediate signal using a non-CABAC decoding standard. A buffer is provided between the first and second processing circuits to improve processing speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.