High performance programmable cryptography system
US7840000B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Oct 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and system for high performance programmable cryptography. In an embodiment of the invention, a cryptography system in accordance with the present invention may include a processor with memory, at least two field programmable gate array (FPGA) blocks and control logic which may be algorithm independent. Programming files storing one or more crypto algorithms may be maintained remotely to the cryptography system whereby the cryptography system may remain not cryptographically controlled when un-programmed. FPGA blocks may be field-programmed to allow execution of a desired crypto algorithm. Additionally, with multiple FPGA logic blocks, programming of a first FPGA block may be simultaneously performed with the execution of a crypto algorithm via a second FPGA block to enable enhanced encryption rate performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.