Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit
US7840727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Oct 31, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided multi-phase clock signals from a counter. The selector receives the parallel data from the register to select one of the data in accordance with a control signal. The counter generates the control signal for the selector so that plural items of data will be output serially from the selector in the sequence in which the plural items data have been serially supplied to the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.