Stacked card address assignment
US7840732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Apr 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4095
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Stacking of electronics modules, boards or cards, hereinafter referred to as cards is described. Each card in a stack is connected logically to a host via a single physical bus slot, and can detect its relative position in the stack on initial power on and make use of that information to grab an appropriate resource pool. In one embodiment, a top most card is used as a reference and the rest of the cards in the stack derive a relative address with respect to the top most card. A few lines are dedicated between neighboring cards through which the cards can share their relative address information with succeeding cards and automate resource allocation based on the address information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.