Simple bus buffer
US7840734B2 · kind B2 · utility
9Cited by
16References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Dec 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.