Translated memory protection apparatus for an advanced microprocessor
US7840776B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Oct 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.