Method for autonomous dynamic voltage and frequency scaling of microprocessors

US7840825B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Peter Altevogt · Ettlingen, DE
• Hans Boettiger · Lörrach, DE
• Wesley M. Felter · Austin, US
• Charles R. Lefurgy · Austin, US
• Lutz Stiege · Lüneburg, DE
• Malcolm S. Ware · Raleigh, US

Key dates

• Filing date: Aug 14, 2007
• Grant date: Nov 23, 2010
• Expiry date: Aug 27, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for autonomous dynamic voltage (v) and frequency (f) scaling (DVFS) of a microprocessor, wherein autonomous detection of phases of high microprocessor workload and prediction of their duration is performed (PID). The microprocessor frequency (f) will be temporarily increased (LUT) to an appropriate safe value (even beyond its nominal frequency) consistent with technological and ambient constraints in order to improve performance when the computer system comprising the microprocessor benefits most, while during phases of low microprocessor workload its frequency (f) and voltage (v) will be decreased to save energy. This technique exploits hidden performance capabilities and improves the total performance of a computer system without compromising operational stability. No additional hardware such as service processors is needed for contemporary computer systems supporting performance counters and DFVS already. The invention allows significantly increasing the total computer system performance with only minimal impact on power (PMAX, PACTUAL) consumption.