Power savings for memory with error correction mode
US7840876B2 · kind B2 · utility
11Cited by
17References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Sep 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.