Methods and apparatus for error checking code computation
US7840880B1 · kind B1 · utility
24Cited by
5References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Aug 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for more efficiently computing error checking codes such as cyclic redundancy checks (CRCs). Based on particular characteristics of CRCs, an input sequence is intelligently divided into a series of subsequences. Each subsequence gets selected bits from the input sequence. The error checking code is calculated on each subsequence. The results are bit-interleaved and an error checking code is calculated over this interleaved result to obtain the error checking code over the entire sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.