Methods and apparatuses for designing integrated circuits using virtual cells
US7840923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Dec 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for analyzing and/or designing integrated circuits using virtual transparent cells disclosed. Some embodiments comprise calculating model values for virtual transparent cells or elements of an integrated circuit design varying a transparency variable in modeling equations, and allowing replacement of the cell with a wire based upon the calculations. Varying the value of the transparency value for the calculations may allow the virtual transparent cells to be continuously modeled between a wire and a conventional version of the cell. Some embodiments may comprise a cell library with one or more modeling formulas for one or more virtual transparent cells and a response module to calculate different model values of the modeling formulas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.