Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices
US7842591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2008 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Dec 3, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
Abstract
A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.