Nonvolatile semiconductor memory device having floating gate that includes two layers
US7842992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Jun 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.