Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom
US7843721B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2008 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.