System and method for better testability of OTP memory
US7843747B2 · kind B2 · utility
10Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2008 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Jan 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.