Method and system for error correction in flash memory
US7844879B2 · kind B2 · utility
56Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Sep 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/563
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.