Method for designing a semiconductor integrated circuit layout capable of reducing the processing time for optical proximity effect correction
US7844934B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 14, 2006 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Jul 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.