Nanoimprint enhanced resist spacer patterning method
US7846756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2008 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Mar 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.