Multi-thickness semiconductor with fully depleted devices and photonic integration
US7847353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2008 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.