Algorithmic analog-to-digital converter
US7847713B2 · kind B2 · utility
1Cited by
12References
9Claims
0Family size
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Key dates
| Filing date | Apr 30, 2009 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | May 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.