Frequency synthesizers for wireless communication systems
US7848266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2008 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Apr 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Synthesizers are configured with first and second phase-locked loops (PLL's). The first PLL is arranged to include a digitally-controlled oscillator (DCO) and to respond to an input signal to provide a reference signal with a plurality of selectable reference frequencies. The second PLL is arranged to include a voltage-controlled oscillator (VCO) to thereby provide output signals in response to the reference signal. This synthesizer structure is particularly effective when responding to a noisy input signal as may be the case, for example, in wireless communication systems that provide a network clock to transceivers through lengthy optical links.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.