Highly integrated, high-speed, low-power serdes and systems
US7848367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Oct 13, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/907
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.