Synchronization method of data interchange of a communication network, and corresponding circuit and architecture
US7848472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2004 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Feb 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (4). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.