Pipeline-based reconfigurable mixed-radix FFT processor
US7849123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2007 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Aug 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.