Patent · US Active

DDR control

US7849345B1 · kind B1 · utility

9Cited by

3References

16Claims

0Family size

Assignee

Marvell International Ltd. · BM

Inventors

Jitendra Kumar Swarnkar · Sunnyvale, US
Jie Du · Medford, US
Vincent Wong · معلمی نژاد, US

Key dates

Filing date	Oct 26, 2007
Grant date	Dec 7, 2010
Priority date	—
Expiry date	Jul 24, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/1689
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system clock. A second register, coupled to the first register, captures the output of the first register based on the rising edge of the system clock. A third register, captures the upper data word based on the falling edge of the system clock. A forth register, coupled to the third register, captures the output of the third register based on the falling edge of the system clock. A first multiplexer is coupled to a forth register and a second register. A delay element, coupled to the system clock and a first multiplexer, adjusts the phase of the system clock. A second multiplexer, coupled to the system clock, generates a data strobe.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.