Programmable delay clock buffer
US7849348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2007 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Jun 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.