Responding to a storage processor failure with continued write caching
US7849350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Oct 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique responds to a storage processor failure. The technique involves performing write-back caching operations using a cache of a first storage processor, and mirroring data from the cache of the first storage processor to a cache of a second storage processor. The technique further involves, after of a failure of the second storage processor in which the second storage processor becomes unavailable, continuing to perform write-back caching operations using the cache of the first storage processor while the second storage processor remains unavailable. A cache controller is capable of being modified so that any write data in the cache of the first storage processor persists if the first storage processor encounters a failure thus preventing loss of the cached write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.