Memory control circuit, nonvolatile storage apparatus, and memory control method
US7849382B2 · kind B2 · utility
7Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2005 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Nov 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.