Stack-type semiconductor package, method of forming the same and electronic system including the same
US7851259B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a stack-type semiconductor package includes preparing a lower printed circuit board including a plurality of interconnections and a plurality of ball lands for connection on an upper surface thereof. One or more first chips, which are electrically connected to the plurality of interconnections and sequentially stacked, are mounted on the lower printed circuit board. A lower molded resin compound is formed on the lower printed circuit board to cover the first chips, and is formed to have via holes exposing the ball lands for connection. An upper chip package, under which solder balls are formed, is aligned so that the solder balls correspond to the via holes of the lower molded resin compound, respectively. The solder balls are reflown to form connection conductors filling the via holes. A stack-type semiconductor package structure and an electronic system including the same are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.