Multichip package or system-in package
US7851898B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Sep 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.