Power-efficient biasing circuit
US7852168B1 · kind B1 · utility
7Cited by
4References
64Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2007 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0802
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Energy-efficient timing circuits are described. Such circuits may include a biasing circuit configured to provide a control bias current to a voltage-controlled oscillator (VCO). The biasing circuit may repetitively switch between a normal-power operating mode and a reduced-power operating mode. During the normal-power operating mode, the biasing circuit may generate a control voltage representative of a desired control bias current for the VCO. By then storing the control voltage using a device, such as a capacitor, much of the biasing circuit may be turned off during the reduced-power operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.