Multi-chip package for a flash memory
US7852690B2 · kind B2 · utility
7Cited by
61References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Jun 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5643
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system includes a flash memory die having multiple flash memory cells. Each flash memory cell is operable to store at least four bits of data. A second die includes a controller for accessing the flash memory cells. DRAM is used by the controller to temporarily store data. An interface is operable to send and receive signals associated with the flash memory cells to a host. A housing contains the flash memory die, the second die, the DRAM, and the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.