High-speed receiver architecture
US7852913B2 · kind B2 · utility
16Cited by
14References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 14, 2006 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Feb 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.