Parallel testing in a per-pin hardware architecture platform
US7853425B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Apr 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31907
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.